Design and Analysis of an Ultra Low Power Clocked Regenerative Comparator
نویسندگان
چکیده
This paper explores various available comparator designs and proposes an improved ultra low power comparator with reduced delay at 90nm. Dynamic comparators which are extensively used in data converters and digital signal processors require low power consumption and high speed. A clock based dynamic comparator is simulated with delay of 64ps and power dissipation of 31.8μW. The comparator structure is designed using tanner EDA. A comparative simulated analysis of various comparators shows that the proposed design is more power efficient and have 73% less delay. Keywords— delay, comparator, low power, latch
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